[0.100.5] CVS commit

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[0.100.5] CVS commit

Jussi Laako
Hi,

Today I committed the SSE/E3DNow mixing support to the CVS. There's new
config option --enable-dynsimd to enable it. It is disabled by default.

gcc-4.x may need "-msse -m3dnow" compiler options to compile if -march
isn't high enough to include those. Someone who is familiar enough with
autotools could add autodetection for this.

ChangeLog entry:

2005-09-04 22:50  sonarnerd
 
        * configure.ac, jack/intsimd.h, libjack/client.c,
libjack/port.c:
          SSE and E3DNow! mixing support with new config option
          --enable-dynsimd


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Re: [0.100.5] CVS commit

Leonard Ritter-2
cool! have you done some benchmarking?

On Sunday 04 September 2005 21:58, Jussi Laako wrote:

> Hi,
>
> Today I committed the SSE/E3DNow mixing support to the CVS. There's new
> config option --enable-dynsimd to enable it. It is disabled by default.
>
> gcc-4.x may need "-msse -m3dnow" compiler options to compile if -march
> isn't high enough to include those. Someone who is familiar enough with
> autotools could add autodetection for this.
>
> ChangeLog entry:
>
> 2005-09-04 22:50  sonarnerd
>
>         * configure.ac, jack/intsimd.h, libjack/client.c,
> libjack/port.c:
>           SSE and E3DNow! mixing support with new config option
>           --enable-dynsimd

--
-- leonard "paniq" ritter
-- http://www.paniq.org
-- http://www.mjoo.org


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Re: [0.100.5] CVS commit

Jussi Laako
On Sun, 2005-09-04 at 22:42 +0200, Leonard "paniq" Ritter wrote:
> cool! have you done some benchmarking?

Yes, I already posted some results earlier. Here's that part of the
previous post:

... using 32 channels and period size 1024:

P4/3000z (Prescott), using SSE code:
gen_mix(): 81.6106 us
x86_mix(): 24.4454 us

Athlon XP 2400+, using E3DNow! code:
gen_mix(): 138.091 us
x86_mix(): 89.7967 us

Compile flags used: "-march=i686 -O3 -ffast-math"


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Re: [0.100.5] CVS commit

Leonard Ritter-2
hmm.... what are the numbers like without accelleration? ;)

On Mon, 2005-09-05 at 00:32 +0300, Jussi Laako wrote:

> On Sun, 2005-09-04 at 22:42 +0200, Leonard "paniq" Ritter wrote:
> > cool! have you done some benchmarking?
>
> Yes, I already posted some results earlier. Here's that part of the
> previous post:
>
> ... using 32 channels and period size 1024:
>
> P4/3000z (Prescott), using SSE code:
> gen_mix(): 81.6106 us
> x86_mix(): 24.4454 us
>
> Athlon XP 2400+, using E3DNow! code:
> gen_mix(): 138.091 us
> x86_mix(): 89.7967 us
>
> Compile flags used: "-march=i686 -O3 -ffast-math"
>
>



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Re: [0.100.5] CVS commit

Jussi Laako
On Mon, 2005-09-05 at 09:35 +0200, Leonard "paniq" Ritter wrote:
> hmm.... what are the numbers like without accelleration? ;)

gen_mix() is the original jack code. x86_mix() is the new SIMD one.


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Re: [0.100.5] CVS commit

Paul Davis
In reply to this post by Jussi Laako
On Sun, 2005-09-04 at 22:58 +0300, Jussi Laako wrote:
> Hi,
>
> Today I committed the SSE/E3DNow mixing support to the CVS. There's new
> config option --enable-dynsimd to enable it. It is disabled by default.

i like these patches, and they've inspired a dramatic performance
improvement in ardour by selectively applying SSE routines for specific
functions in ardour.

but AFAICT, your detection routines do not work. sampo copied them into
ardour for use with his stuff, and found immediate problems, mostly
caused by interactions between inline asm and gcc. on my system, if i
document what happens in init_cpu(), i get:

    have 3dnow? 0 sse? 0
    Will use generic mix routines

this is on a P4 that is happily using SSE inside of ardour. sampo ended
up just taking the cpuid value and checking the flags, but he had to (a)
drop %ebx from the clobber list (PIC code uses it) and (b) push/pop %ebx
(same reason). as far as we know, it works on P2...P4+AMD

> gcc-4.x may need "-msse -m3dnow" compiler options to compile if -march
> isn't high enough to include those. Someone who is familiar enough with
> autotools could add autodetection for this.

this has been taken care of in other ways, because of changes i've made
to how optimization flags are chosen/defined.

--p




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Re: [0.100.5] CVS commit

Jussi Laako
On Fri, 2005-09-09 at 23:26 -0400, Paul Davis wrote:
> document what happens in init_cpu(), i get:
>     have 3dnow? 0 sse? 0
>     Will use generic mix routines

I committed detection printout code to the CVS. It should print
"Detected Enhanced3DNow!" or "Detected SSE2" to stderr depending on CPU.
I re-tested things and it works here. If it doesn't work for someone
else, please quote used compiler and flags so I can try to reproduce
this and fix it.


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Re: [0.100.5] CVS commit

Jussi Laako
In reply to this post by Paul Davis
On Fri, 2005-09-09 at 23:26 -0400, Paul Davis wrote:
> i like these patches, and they've inspired a dramatic performance
> improvement in ardour by selectively applying SSE routines for
> specific
> functions in ardour.

SSE is the only way to get full performance out of recent CPUs,
especially x86-64 when it comes to float operations. Especially memory
access is otherwise the bottleneck.

It's also very important to have 16-byte data alignment as much as
possible. Intel CPU's speed drops about 50% when doing unaligned memory
access. AMD ones don't care that much with performance hit of about 1-2%
or something similar. Even g++-4.x doesn't seem to do proper alignment
with new operator for float types, which is sad. So posix_memalign() is
the only way to go. For this (and other) reason(s) I have "clAlloc"
class to do memory allocations in C++.

> up just taking the cpuid value and checking the flags, but he had to (a)
> drop %ebx from the clobber list (PIC code uses it) and (b) push/pop %ebx
> (same reason). as far as we know, it works on P2...P4+AMD

Yes, also the code I committed saves EBX as it should. It just tests
feature bits inside the asm code. If there is some problem with the
current code I would very much like to inspect what it is.

Mixing code should be also compatible with x86-64, both 3DNow and SSE
should work on AMD64, SSE works on IA32EMT. The detection code can be
disabled there with just cpu_type = 0x2. However, as I don't currently
have the hardware to test it, I don't commit such feature.

I have tested the code in P4 (Prescott core with SSE3) and Athlon XP
(Barton core?).

Here's the relevant information for my case:

SuSE 9.2 gcc: gcc (GCC) 3.3.4 (pre 3.3.5 20040809)
and: gcc (GCC) 4.0.1

Compiler flags:
gcc-3.x: "-march=i686 -O2 -ffast-math"
gcc-4.x: "-march=prescott -O2 -ffast-math"

vendor_id       : GenuineIntel
cpu family      : 15
model           : 3
model name      : Intel(R) Pentium(R) 4 CPU 3.00GHz
stepping        : 3
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni
monitor ds_cpl cid

vendor_id       : AuthenticAMD
cpu family      : 6
model           : 10
model name      : AMD Athlon(tm) XP  2400+
stepping        : 0
flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca
cmov pat pse36 mmx fxsr sse pni syscall mmxext 3dnowext 3dnow


NOTE: kernel on P4 doesn't show SSE3 as it's SuSE's "2.6.8-24.18-smp".
Hopefully more recent ones do show... ;)

Athlon is running more recent SuSE 9.3 with "2.6.11.4-21.8-default".


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Re: [0.100.5] CVS commit

Paul Davis
In reply to this post by Jussi Laako
On Sat, 2005-09-10 at 11:15 +0300, Jussi Laako wrote:

> On Fri, 2005-09-09 at 23:26 -0400, Paul Davis wrote:
> > document what happens in init_cpu(), i get:
> >     have 3dnow? 0 sse? 0
> >     Will use generic mix routines
>
> I committed detection printout code to the CVS. It should print
> "Detected Enhanced3DNow!" or "Detected SSE2" to stderr depending on CPU.
> I re-tested things and it works here. If it doesn't work for someone
> else, please quote used compiler and flags so I can try to reproduce
> this and fix it.

it doesn't print out anything on my system.

i don't believe this is a problem with your assembler. from the work
that sampo did with this, its because of an interaction between gcc and
the inline asm. it fails to return the correct value with some versions
of gcc.

i am using gcc 3.4.4; what are you using?

--p




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Re: [0.100.5] CVS commit

Lee Revell
On Sat, 2005-09-10 at 08:37 -0400, Paul Davis wrote:

> On Sat, 2005-09-10 at 11:15 +0300, Jussi Laako wrote:
> > On Fri, 2005-09-09 at 23:26 -0400, Paul Davis wrote:
> > > document what happens in init_cpu(), i get:
> > >     have 3dnow? 0 sse? 0
> > >     Will use generic mix routines
> >
> > I committed detection printout code to the CVS. It should print
> > "Detected Enhanced3DNow!" or "Detected SSE2" to stderr depending on CPU.
> > I re-tested things and it works here. If it doesn't work for someone
> > else, please quote used compiler and flags so I can try to reproduce
> > this and fix it.
>
> it doesn't print out anything on my system.
>
> i don't believe this is a problem with your assembler. from the work
> that sampo did with this, its because of an interaction between gcc and
> the inline asm. it fails to return the correct value with some versions
> of gcc.

Why are you trying to guess the CPU features rather than just
reading /proc/cpuinfo?

Lee



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Re: [0.100.5] CVS commit

Paul Davis
> > i don't believe this is a problem with your assembler. from the work
> > that sampo did with this, its because of an interaction between gcc and
> > the inline asm. it fails to return the correct value with some versions
> > of gcc.
>
> Why are you trying to guess the CPU features rather than just
> reading /proc/cpuinfo?

we're not guessing. we're masking the value stored in a register by the
cpuid instruction with the specific flag for SSE support. maybe 5000
times faster than reading /proc/cpuinfo, which does the same thing :)

--p




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Re: [0.100.5] CVS commit

Tim Blechmann
In reply to this post by Lee Revell
> Why are you trying to guess the CPU features rather than just
> reading /proc/cpuinfo?
maybe because there are a systems, that don't have /proc/cpuinfo?

for pure data implementing an simd (sse) check was as easy as this:

int simd_runtime_check()
{
    unsigned int eax, edx;
    __asm__("push %%ebx \n"
            "cpuid      \n"
            "pop  %%ebx \n"
                : "=a"(eax),"=d"(edx) : "a" (1): "cx");
    return (0x2000000 & edx);
}

this is working on all x86 systems, that have a gcc compiler ... linux,
osx (when they'll switch to intel cpus) and windoze ...

and it's easily portable to m$vc:
int simd_runtime_check()
{
    unsigned int redx;
    __asm
        {
                mov eax, 1
                push    ebx
                cpuid
                pop     ebx
            mov [redx],edx    
        }
    return (0x2000000 & redx);
}

cheers ... tim

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Re: [0.100.5] CVS commit

Lee Revell
On Sat, 2005-09-10 at 21:00 +0000, Tim Blechmann wrote:

> > Why are you trying to guess the CPU features rather than just
> > reading /proc/cpuinfo?
> maybe because there are a systems, that don't have /proc/cpuinfo?
>
> for pure data implementing an simd (sse) check was as easy as this:
>
> int simd_runtime_check()
> {
>     unsigned int eax, edx;
>     __asm__("push %%ebx \n"
>             "cpuid      \n"
>             "pop  %%ebx \n"
> : "=a"(eax),"=d"(edx) : "a" (1): "cx");
>     return (0x2000000 & edx);
> }
>
> this is working on all x86 systems, that have a gcc compiler ... linux,
> osx (when they'll switch to intel cpus) and windoze ...

OK, I guess it just feels to me like this should live in some library or
command line utility or some other high level interface, rather than
being in JACK.

Lee



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Re: [0.100.5] CVS commit

Sampo Savolainen
In reply to this post by Tim Blechmann
On Sat, 2005-09-10 at 21:00 +0000, Tim Blechmann wrote:

> for pure data implementing an simd (sse) check was as easy as this:
>
> int simd_runtime_check()
> {
>     unsigned int eax, edx;
>     __asm__("push %%ebx \n"
>             "cpuid      \n"
>             "pop  %%ebx \n"
> : "=a"(eax),"=d"(edx) : "a" (1): "cx");
>     return (0x2000000 & edx);
> }

This is what Paul and I thought would work. Sadly, it isn't enough. It
seems gcc isn't smart enough to understand that the value of %edx
actually changes. Or more specifically, gcc's optimizer doesn't
understand that %edx changes.

This is what I came up with:

unsigned int use_sse = 0;

asm volatile (
        "mov $1, %%eax\n"
        "pushl %%ebx\n"
        "cpuid\n"
        "popl %%ebx\n"
        "andl $33554432, %%edx\n"
        "movl %%edx, %0\n"
        : "=m" (use_sse)
        :
  : "%eax", "%ecx", "%edx", "memory");

I guess what makes this work is that there is the "andl" instruction
which modifies %edx. For paranoia's sake, we move %edx to the memory
"register" use_sse.

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Re: [0.100.5] CVS commit

Jussi Laako
On Sat, 2005-09-10 at 22:17 +0300, Sampo Savolainen wrote:
> This is what Paul and I thought would work. Sadly, it isn't enough. It
> seems gcc isn't smart enough to understand that the value of %edx
> actually changes. Or more specifically, gcc's optimizer doesn't
> understand that %edx changes.

OK, I was not able to make attached source miscompile on any gcc I have.

gcc (GCC) 3.3.4 (pre 3.3.5 20040809)
ogcc (GCC) 3.4.4
ngcc (GCC) 4.0.1

I would like to know how to make it miscompile, so I would have some
idea what breaks and how.


BR,

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Re: [0.100.5] CVS commit

Lee Revell
On Sat, 2005-09-10 at 23:26 +0300, Jussi Laako wrote:

> On Sat, 2005-09-10 at 22:17 +0300, Sampo Savolainen wrote:
> > This is what Paul and I thought would work. Sadly, it isn't enough. It
> > seems gcc isn't smart enough to understand that the value of %edx
> > actually changes. Or more specifically, gcc's optimizer doesn't
> > understand that %edx changes.
>
> OK, I was not able to make attached source miscompile on any gcc I have.
>
> gcc (GCC) 3.3.4 (pre 3.3.5 20040809)
> ogcc (GCC) 3.4.4
> ngcc (GCC) 4.0.1
>
> I would like to know how to make it miscompile, so I would have some
> idea what breaks and how.

I guess you tried all levels of optimization?

Lee



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Re: [0.100.5] CVS commit

Tim Blechmann
In reply to this post by Jussi Laako
> OK, I was not able to make attached source miscompile on any gcc I
> have.
>
> gcc (GCC) 3.3.4 (pre 3.3.5 20040809)
> ogcc (GCC) 3.4.4
> ngcc (GCC) 4.0.1
>
> I would like to know how to make it miscompile, so I would have some
> idea what breaks and how.

me too ... i did some tests with gcc version 3.4.4 with different
cflags ... the assembly code looked pretty good ...

i'm pretty curious, how to miscompile this, since i've been using this
code for at least one year now ... never heard any bad feedback about
this ...

cheers ... tim

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